Srinivasan, Prakash and Farrell, Ronan and Ward, Eamon (2008) Modular Scan Test for SoC Design. In: Intel European Research and Innovation Conference, 10-12 September 2008 , Leixlip, Ireland .

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Abstract

In this paper we try to reconfigure the existing scan system to a Modular Scan (MS) in order to adapt itself for future complexities of the chip design. One specific application of MS is the Multiprocessor System-on-Chip (MPSoC) design, where each core can have its own scan chain and also have concurrent testing procedure. MS is a process of arranging the scan chains flexibly for multiple usages during scan test. MS can be used in large chip designs to reduce the length of scan chains, and to reduce the testing time. MS based tests allow the test engineer to easily reconstruct the scan chain in an MPSoC design, if any of the existing cores needs to be replaced with a new core in order to meet the new set of specifications. To achieve such a type of testing, generic scan chain architecture needs to be developed in order to ensure an easy plug-n-play scan chain in the system architecture.

Item Type:	Conference or Workshop Item (Paper)
Keywords:	Modular Scan Test; SoC Design;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering
Item ID:	1399
Depositing User:	Ronan Farrell
Date Deposited:	26 May 2009 13:17
Refereed:	Yes
URI:
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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