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    Design Of High Frequency Digital Phase Locked Loops


    Daniels, Brian and Farrell, Ronan (2006) Design Of High Frequency Digital Phase Locked Loops. In: UNSPECIFIED.

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    Abstract

    This paper considers the stability of high order Charge Pump Phase Lock Loop (CP-PLL), proposing a novel means of identifying stable regions for such systems. Traditional design techniques are inefficient for high frequency, high order CPPLL systems. This paper proposes an accurate and efficient means of identifying stable regions for 2nd and 3rd order high frequency (> 1GHz) CP-PLL. Using exact non-linear CP-PLL responses it is shown that the proposed stability technique is a significant improvement over existing linear methods.

    Item Type: Conference or Workshop Item (Paper)
    Additional Information: This paper is a postprint of a paper submitted to and accepted for publicatin in (journal/conference) and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library
    Keywords: Stability, Charge Pump, Phase Locked Loop, High Frequency.
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Item ID: 601
    Depositing User: Dr. Ronan Farrell
    Date Deposited: 12 Jul 2007
    Publisher: Institution of Engineering and Technology
    Refereed: Yes
    URI:

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