MURAL - Maynooth University Research Archive Library



    Virtual Machine Showdown: Stack Versus Registers


    Shi, Yunhe and Casey, Kevin and Ertl, Anton and Gregg, David (2008) Virtual Machine Showdown: Stack Versus Registers. ACM Transactions on Architecture and Code Optimization (TACO), 4 (4:21). ISSN 1544-3566

    [img]
    Preview
    Download (2MB) | Preview


    Share your research

    Twitter Facebook LinkedIn GooglePlus Email more...



    Add this article to your Mendeley library


    Abstract

    Virtual machines (VMs) enable the distribution of programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the design of VMs is whether a stack architecture or register architecture can be implemented more efficiently with an interpreter. We extend existing work on comparing virtual stack and virtual register architectures in three ways. First, our translation from stack to register code and optimization are much more sophisticated. The result is that we eliminate an average of more than 46% of executed VM instructions, with the bytecode size of the register machine being only 26% larger than that of the corresponding stack one. Second, we present a fully functional virtual-register implementation of the Java virtual machine (JVM), which supports Intel, AMD64, PowerPC and Alpha processors. This register VM supports inline-threaded, direct-threaded, token-threaded, and switch dispatch. Third, we present experimental results on a range of additional optimizations such as register allocation and elimination of redundant heap loads. On the AMD64 architecture the register machine using switch dispatch achieves an average speedup of 1.48 over the corresponding stack machine. Even using the more efficient inline-threaded dispatch, the register VM achieves a speedup of 1.15 over the equivalent stack-based VM.

    Item Type: Article
    Additional Information: Cite as: Shi, Y. Casey, K., Ertl, M. A., and Gregg, D. 2008. Virtual machine showdown: stack versus registers. ACM Trans. Architec. Code Optim. 4, 4, Article 21 (January 2008). DOI: 10.1145/1328195.1328197 http://doi.acm.org/10.1145/1328195.1328197
    Keywords: Interpreter; virtual machine; register architecture; stack architecture;
    Academic Unit: Faculty of Science and Engineering > Research Institutes > Hamilton Institute
    Item ID: 10185
    Identification Number: https://doi.org/10.1145/1328195.1328197
    Depositing User: Hamilton Editor
    Date Deposited: 07 Nov 2018 16:19
    Journal or Publication Title: ACM Transactions on Architecture and Code Optimization (TACO)
    Publisher: ACM
    Refereed: Yes
    URI:

    Repository Staff Only(login required)

    View Item Item control page

    Downloads

    Downloads per month over past year