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    Rigorous Stability Criterion for Digital Phase Locked Loops


    Daniels, Brian and Farrell, Ronan (2008) Rigorous Stability Criterion for Digital Phase Locked Loops. ISAST Transactions on Electronics and Signal Processing, 3 (2). pp. 1-10.

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    Abstract

    This paper proposes a rigorous stability criterion for an arbitrary order digital phase locked loop (DPLL), with a charge pump phase frequency detector (CP-PFD) component. Stability boundaries for such systems are determined using piecewise linear methods to model the nonlinear nature of the CP-PFD component block. The model calculates the control voltage, after a predetermined number of input reference signal sampling periods, to a small initial voltage offset. This paper, in particular, takes an in-depth look at the second order system. The second order stability boundaries, as defined by the proposed technique, are compared to that of existing linear theory stability boundaries, and display a significant improvement. The applicability of the proposed technique to higher order systems, using a numerically iterative solution, is presented. Finally the proposed methodology is used to determine the stability boundary of a third order system and thus the component values for a stable system. Using these component values the response of the DPLL to an initial control voltage offset is simulated using a circuit level simulation. Index Terms—High Order, Phase Locked Loop, Piecewise Linear, Stability.

    Item Type: Article
    Keywords: High Order; Phase Locked Loop; Piecewise Linear; Stability;
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Item ID: 1404
    Depositing User: Dr. Ronan Farrell
    Date Deposited: 26 May 2009 13:11
    Journal or Publication Title: ISAST Transactions on Electronics and Signal Processing
    Publisher: The International Society for Advanced Science and Technology (ISAST)
    Refereed: Yes
    URI:

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