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    SPAlink: A Flexible Bitstream Link for Class S-Power Amplifiers


    Astarloa, Armando and Bidarte, Unai and Dooley, John and Canniff, Alan and Farrell, Ronan (2009) SPAlink: A Flexible Bitstream Link for Class S-Power Amplifiers. Applied Electronics, 2009. (AE 2009) Pilsen. pp. 31-36. ISSN 1803-7232

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    Abstract

    In this paper a multi-platform HDL description of a circuit that implements all the digital processing and RF carrier generation for the class S Power Amplifier proposed by the Institute of Microelectronics and Wireless Systems is presented. The circuit is the combination of a lowpass sigma-delta modulation stage in series with a frequency shifting stage that generates the bitstream that drives a switch mode amplifier followed by a bandpass filter. This HDL description is that it can be implemented not only on high-end FPGAs but on low-cost devices as well. The 8 parameters that define at compilation time the final implementation are presented and four implementations are discussed in this work. The design is validated with data measured in the simulation and in the prototype.

    Item Type: Article
    Additional Information: This work has been partially supported by the Government of the Basque Country within the research project IE08-221.
    Keywords: band-pass filters; digital signal processing chips; field programmable gate arrays; hardware description languages; power amplifiers; radiofrequency amplifiers; sigma-delta modulation;
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Faculty of Science and Engineering > Research Institutes > Institute of Microelectronics and Wireless Systems
    Item ID: 2402
    Identification Number: Print ISBN: 978-80-7043-781-0
    Depositing User: Dr. Ronan Farrell
    Date Deposited: 26 Jan 2011 15:31
    Journal or Publication Title: Applied Electronics, 2009. (AE 2009) Pilsen
    Publisher: IEEE
    Refereed: Yes
    Funders: Government of the Basque Country
    URI:

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