Daniels, Brian (2008) Analysis and design of high order digital phase locked loops. PhD thesis, National University of Ireland Maynooth.

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Abstract

The Phase Locked Loop (PLL) is an important component of many electronic devices; it can be employed as a frequency synthesizer, for clock data recovery, and as amplitude and frequency demodulators. It is an inherently nonlinear closed loop feedback system; the nonlinearity is due mainly to the fact that the feedback loop comparator exhibits quantization-like effects at its output. The consequence of this nonlinearity is a lack of understanding of the behaviour of the PLL loop, particularly the behaviour and stability of high order PLL systems. This thesis presents a new design technique for high order Digital PLL (DPLL)systems with a charge pump phase frequency detector component, offering an alternative to the common design practice which is to analyze the DPLL using a linearised model of the analogue PLL. The linear model can only be justified for low order DPLL systems that are close to lock. This is due to the fact that as the DPLL systems loop order and complexity increases the linear model becomes increasingly inaccurate, thus high orders are considered risky. The benefit of a high order DPLL loop is a purer output signal with less jitter and therefore better spectral efficiency making them highly desirable. The design of high order DPLL systems is realised here by utilising three novel design techniques. First, the complexity of the high order system equation is reduced by introducing an approximation of charge on the loop filter capacitors. Second, the nonlinearity is modelled using a piecewise linear model, thus the complexity of the model is further reduced by determining the system stability and lock time from only the first few samples in state space. Finally, to reduce the number of design variables that are required as the loop order is increased, filter prototypes, which only require one parameter, are introduced with the result of optimally placing the system poles. The consequence of implementing the above methodologies is that the mathematical restriction on the system order can be overcome and the stability of high order DPLL systems can be accurately determined.

Item Type:	Thesis (PhD)
Keywords:	Phase locked loop (PLL) ; High order digital phased locked loop(DPLL).
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering
Item ID:	1492
Depositing User:	IR eTheses
Date Deposited:	29 Jul 2009 16:46
URI:
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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