Nardo, Lucas and Nepomuceno, Erivelton and Muñoz, Daniel and Butusov, Denis and Arias-Garcia, Janier (2023) A Hardware-Efficient Perturbation Method to the Digital Tent Map. Electronics, 12 (8). p. 1953. ISSN 2079-9292

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Abstract

Digital chaotic systems used in various applications such as signal processing, artificial intelligence, and communications often suffer from the issue of dynamical degradation. This paper proposes a solution to address this problem in the digital tent map. Our proposed method includes a simple and optimized hardware architecture, along with a hardware-efficient perturbation method, to create a high-performance computing system that retains its chaotic properties. We implemented our proposed architecture using an FPGA (Field-Programmable Gate Array) and the 1’s complement fixed-point format. Our results demonstrate that the implemented digital circuit reduces logical resource consumption compared to state-of-the-art references and exhibits pseudo-random nature, as confirmed by various statistical tests. We validated our proposed pseudo-random number generator in a hardware architecture for particle swarm optimization, demonstrating its effectiveness.

Item Type:	Article
Keywords:	chaotic map; computer arithmetic; digital system; hardware architecture; pseudo-random number generator; particle swarm optimization;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering
Item ID:	18534
Identification Number:	https://doi.org/10.3390/electronics12081953
Depositing User:	Erivelton Nepomuceno
Date Deposited:	16 May 2024 14:01
Journal or Publication Title:	Electronics
Publisher:	MDPI
Refereed:	Yes
URI:	Publisher
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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