Collins, Diarmuid and Keady, Aidan and Szczepkowski, Grzegorz and Farrell, Ronan (2011) Fast Digital Calibration of Static Phase Offset in Charge-Pump Phase-Locked Loops. In: ISSC 2011, June 23-24 2011, Trinity College Dublin.

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Abstract

Mismatches within the charge pump (CP) deteriorate the spectral perfor- mance of the CP-PLL output signal resulting in a static phase offset. Classical analog approaches to reducing this offset consume large silicon area and increase gate leak- age mismatch. For ultra-deep-submicron (UDSM) technologies where gate leakage in- creases dramatically, reduction of static phase offset through digital calibration becomes more favorable. This paper presents a novel technique which digitally calibrates static phase offset down to < 10 ps for a PLL operating at 4.8 GHz, designed using a 1V 90nm CMOS process. Calibration is completed in only 2 steps, making the proposed technique suitable for systems requiring frequent switching such as frequency hopping systems commonly used in today’s wireless communication systems.

Item Type:	Conference or Workshop Item (Paper)
Keywords:	Phase-locked loop (PLL); charge pump (CP); calibration; static phase offset;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering
Item ID:	3680
Depositing User:	Ronan Farrell
Date Deposited:	23 May 2012 16:11
Refereed:	Yes
URI:
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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