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    Benchmarking CMOS Adder Structures

    Schwarzbacher, Andreas and Silvennoinen, J and Timoney, Joseph (2002) Benchmarking CMOS Adder Structures. In: Irish Signals and Systems Conference 2002, June 24-26 2002, Cork, Ireland.

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    Adders are key components in digital signal processing, performing not only addition operations, but also many other functions such as subtraction, multiplication and division. The difficulty with comparing adder structures from different sources is that quite often different implementation techniques and technologies have been used in the design. A second problem that arises when comparing structures is that several different measurement techniques may have been used, the target technology can differ and key features may not been measured. Therefore, this paper will investigate the seven most commonly used adder structures in a way which makes them directly comparable. This is achieved by implementing all adder structures with the same technology, the same level of abstraction and then using the same set of tools to determine the features of each of the designs.

    Item Type: Conference or Workshop Item (Paper)
    Keywords: Adder Structures; High-Level CMOS Design; Ripple Adder; Transmission Gate Adder; Carry-Skip Adder; Carry Look Ahead Adder; Carry Select Adder; Conditional Carry Adder; Conditional Sum Adder; Carry Save Adder; Tree Adder; Chain Adder;
    Academic Unit: Faculty of Science and Engineering > Computer Science
    Faculty of Science and Engineering > Electronic Engineering
    Item ID: 4134
    Depositing User: Joseph Timoney
    Date Deposited: 31 Jan 2013 09:31
    Refereed: Yes
      Use Licence: This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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