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    An Architecture for a reconfigurable charge-summation based ADC

    Duignan, Nigel and Farrell, Ronan (2005) An Architecture for a reconfigurable charge-summation based ADC. In: UNSPECIFIED.

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    Presented in this paper is a low power, area efficient reconfigurable analog-to-digital (ADC) converter, utilising a charge-summation technique with a switched-capacitor implementation. Using a non-inverting switched-capacitor integrator a staircase ramp is produced using switching capacitors and a fixed reference voltage, as opposed to a linear ramp. The advantage of the charge summation technique is the reduction in power usage as the charging time of the capacitors is small so for most of the sample period the circuit is quiescent. The paper presents the use of this architecture as a reconfigurable ADC for use in a reconfigurable radio.

    Item Type: Conference or Workshop Item (Paper)
    Additional Information: This paper is a postprint of a paper submitted to and accepted for publicatin in (journal/conference) and is subject to Institution of Engineering and Technology Copyright. The copy of record is available at IET Digital Library
    Keywords: Switched-capacitor, charge-summation, linearity, reconfigurable radio.
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Item ID: 595
    Depositing User: Ronan Farrell
    Date Deposited: 12 Jul 2007
    Publisher: Institution of Engineering and Technology
    Refereed: Yes
    Use Licence: This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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