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    Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC

    Zanini, Francesco (2007) Architectural Improvements Towards an Efficient 16-18 Bit 100-200 MSPS ADC. Masters thesis, National University of Ireland Maynooth.

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    As Data conversion systems continue to improve in speed and resolution, increasing demands are placed on the performance of high-speed Analog to Digital Conversion systems. This work makes a survey about all these and proposes a suitable architecture in order to achieve the desired specifications of 100-200MS/s with 16-18 bit of resolution. The main architecture is based on paralleled structures in order to achieve high sampling rate and at the same time high resolution. In order to solve problems related to Time-interleaved architectures, an advanced randomization method was introduced. It combines randomization and spectral shaping of mismatches. With a simple low-pass filter the method can, compared to conventional randomization algorithms, improve the SFDR as well as the SINAD. The main advantage of this technique over previous ones is that, because the algorithm only need that ADCs are ordered basing on their time mismatches, the absolute accuracy of the mismatch identification method does not matter and, therefore, the requirements on the timing mismatch identification are very low. In addition to that, this correction system uses very simple algorithms able to correct not only for time but also for gain and offset mismatches.

    Item Type: Thesis (Masters)
    Keywords: ADC architecture; 16-18 Bit 100-200 MSPS ADC;
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Item ID: 740
    Depositing User: Francesco Zanini
    Date Deposited: 17 Oct 2007
    Refereed: No
      Use Licence: This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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