Srinivasan, Prakash and Farrell, Ronan (2010) Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT. In: IEEE Computer Society Annual Symposium on VLSI, 2010. IEEE, pp. 52-57. ISBN 9781424473212

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Abstract

Modular and hierarchical based test architecture are the two of the most common testing techniques used in complex SoC designs. However, modular test architectures uses an expensive (in terms of silicon area) test wrapper around each block. On the other hand hierarchical test architecture requires additional effort at block level to isolate each block from surrounding blocks and a TAM to perform scan compression. In this paper, we analyze the limitations of the modular test architecture. Based on the analysis, we propose a test plan for hierarchical test architecture by integrating partition chain, combinational scan compression and (RPCT) reduced pin count test. Experimental results show that approximately 50% of DFT area can be reduced using the partition chain as compared to standard test wrapper. It also demonstrates the feasibility of the proposed test plan using a commercial ATPG tool.

Item Type:	Book Section
Keywords:	hierarchical design for testability; combinational scan compression; partition chain; RPCT; SoC designs; modular test architectures; test wrapper; hierarchical test architecture; ATPG;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering Faculty of Science and Engineering > Research Institutes > Institute of Microelectronics and Wireless Systems
Item ID:	9639
Identification Number:	https://doi.org/10.1109/ISVLSI.2010.59
Depositing User:	Ronan Farrell
Date Deposited:	04 Jul 2018 14:55
Publisher:	IEEE
Refereed:	Yes
URI:	https://ieeexplore.ieee.org
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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