Wu, Fangzhou and Villing, Rudi (2016) FPGA Based FRM GDFT Filter Banks. In: 27th Irish Signals and Systems Conference (ISSC), 2016. IEEE. ISBN 9781509034093

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Abstract

Efficient channelization in flexible, reconfigurable communications systems is an ongoing challenge. Previous work in our lab has shown that designs based on the GDFT-FB (Generalized DFT modulated Filter Bank) combined with FRM (Frequency-Response Masking) can reduce prototype filter complexity and improve hardware efficiency, permitting larger scale designs. In this work we examine the design and implementation of the full FRM GDFT-FB and narrowband FRM GDFT-FB on an FPGA and describe solutions to various design issues encountered. We evaluate the DSP performance and the FPGA resource usage using a concrete channelization problem based on TETRA 25 kHz channels.

Item Type:	Book Section
Keywords:	GDFT-FB; filter-bank; FRM; FPGA; polyphase;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering
Item ID:	9770
Identification Number:	https://doi.org/10.1109/ISSC.2016.7528473
Depositing User:	Rudi Villing
Date Deposited:	14 Aug 2018 15:43
Publisher:	IEEE
Refereed:	Yes
URI:	https://ieeexplore.ieee.org
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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