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Burke, K., Power, J.A., Donnellan, Brian, Moloney, K. and Lane, W.A. (1994) Worst-case MOSFET parameter extraction for a 2μm CMOS process. In: Proceedings of 1994 IEEE International Conference on Microelectronic Test Structures. IEEE, pp. 119-125. ISBN 0780317572
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Abstract
This paper will describe the process by which realistic nominal and worstcase DC MOSFFT model parameter sets were determined and validated for
a 2μm CMOS technology. The steps involved in this task, which will be
detailed, ranged from the definition of a suitable circuit simulator model.
through the collection of statistical parametric data, to the generation and
verification of the worstcase model sets obtained from this data.
| Item Type: | Book Section |
|---|---|
| Additional Information: | Cite as: K. Burke, J. A. Power, B. Donnellan, K. Moloney and W. A. Lane, "Worst-case MOSFET parameter extraction for a 2 /spl mu/m CMOS process," Proceedings of 1994 IEEE International Conference on Microelectronic Test Structures, 1994, pp. 119-125, doi: 10.1109/ICMTS.1994.303491. |
| Keywords: | worst-case DC MOSFET model; model parameter sets; CMOS technology; circuit simulator model; statistical parametric data; parameter extraction; 2 micron; |
| Academic Unit: | Faculty of Social Sciences > Research Institutes > Innovation Value Institute, IVI Faculty of Social Sciences > School of Business |
| Item ID: | 14845 |
| Identification Number: | 10.1109/ICMTS.1994 |
| Depositing User: | Prof. Brian Donnellan |
| Date Deposited: | 21 Sep 2021 14:52 |
| Journal or Publication Title: | Proceedings IEEE 1994 Int. Conference on Microelectronic Test Structures |
| Publisher: | IEEE |
| Refereed: | Yes |
| Related URLs: | |
| Use Licence: | This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here |
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