Efficient channelization in flexible, reconfigurable communications systems is an ongoing challenge. Previous work in our lab has shown that designs based on the GDFT-FB (Generalized DFT modulated Filter Bank) combined with FRM (Frequency-Response Masking) can reduce prototype filter complexity and improve hardware efficiency, permitting larger scale designs. In this work we examine the design and implementation of the full FRM GDFT-FB and narrowband FRM GDFT-FB on an FPGA and describe solutions to various design issues encountered. We evaluate the DSP performance and the FPGA resource usage using a concrete channelization problem based on TETRA 25 kHz channels.