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Araujo, TĂșlio and Cardoso, Matheus B.R. and Nepomuceno, Erivelton and Llanos, Carlos H. and Arias-Garcia, Janier (2021) A new floating-point adder FPGA-based implementation using RN-coding of numbers. Computers & Electrical Engineering, 90. p. 106947. ISSN 00457906