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    The case for virtual register machines

    Davis, Brian and Beatty, Andrew and Casey, Kevin and Gregg, David and Waldron, John (2003) The case for virtual register machines. In: IVME '03 Proceedings of the 2003 workshop on Interpreters, virtual machines and emulators. ACM, pp. 41-49. ISBN 1581136552

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    Virtual machines (VMs) are a popular target for language implementers. Conventional wisdom tells us that virtual stack architectures can be implemented with an interpreter more efficiently, since the location of operands is implicit in the stack pointer. In contrast, the operands of register machine instructions must be specified explicitly. In this paper, we present a working system for translating stack-based Java virtual machine (JVM) code to a simple register code. We describe the translation process, the complicated parts of the JVM which make translation more difficult, and the optimisations needed to eliminate copy instructions. Experimental results show that a register format reduces the number of executed instructions by 34.88%, while increasing the number of bytecode loads by an average of 44.81%. Overall, this corresponds to an increase of 2.32 loads for each dispatch removed. We believe that the high cost of dispatches makes register machines attractive even at the cost of increased loads.

    Item Type: Book Section
    Additional Information: This work was supported by Enterprise Ireland Research Innovation Fund, Grant IF/2001/350.
    Keywords: Interpreter; Virtual Machine; Register Architecture; Stack Architecture;
    Academic Unit: Faculty of Science and Engineering > Research Institutes > Hamilton Institute
    Item ID: 10191
    Identification Number:
    Depositing User: Hamilton Editor
    Date Deposited: 08 Nov 2018 15:19
    Publisher: ACM
    Refereed: Yes
    Funders: Enterprise Ireland (EI)
    Use Licence: This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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