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    Digital Pre-distortion Implemented Using FPGA


    Byrne, Declan and Farrell, Ronan and Madhuwantha, Sidath and Dooley, John and Leeser, Miriam (2018) Digital Pre-distortion Implemented Using FPGA. In: 2018 28th International Conference on Field Programmable Logic and Applications (FPL), 27-31 August 2018, Dublin.

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    Abstract

    Massive-MIMO and beamforming techniques have long been proposed as a means of increasing cellular network capacity and improving signal to interference ratio performance. The implementation of such systems requires a large number of signal transmission paths. To realize this, a distributed array of power amplifiers (PAs) is likely to be needed. These PAs will possess similar, but unique, characteristics which will alter over time independently due to temperature drift and component ageing. In order to operate all PAs in both a linear and efficient fashion a linearisation technique, such as Digital Pre-Distortion (DPD), must be used. DPD algorithms benefit from reconfigurability, low latency and power efficiency, all traits associated with Field Programmable Gate Arrays (FPGAs). This demonstration shows how an FPGA, specifically a ZYNQ System on a Chip (SoC), can be used in tandem with a transceiver board, the FMCOMMS2, to implement a DPD system.

    Item Type: Conference or Workshop Item (Paper)
    Additional Information: This publication has emanated from research conducted with the financial support of Science Foundation Ireland (SFI) and is co-funded under the European Regional Development Fund under Grant Number 13/RC/2077.
    Keywords: digital pre-distortion; polynomial evaluation; 5G; FPGA; DSP;
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Faculty of Science and Engineering > Research Institutes > Hamilton Institute
    Item ID: 13334
    Depositing User: Ronan Farrell
    Date Deposited: 30 Sep 2020 15:12
    Refereed: Yes
    Funders: Science Foundation Ireland (SFI), European Regional Development Fund
    URI:

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