Nepomuceno, Erivelton and Lima, Arthur M. and Arias-García, Janier and Perc, Matjaž and Repnik, Robert (2019) Minimal digital chaotic system. Chaos, Solitons & Fractals, 120. pp. 62-66. ISSN 09600779

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Abstract

Over the past few decades, many works have been devoted to designing simple chaotic systems based on analog electronic circuits. However, the same attention is not observed in digital chaotic systems. This paper presents a design of a digital chaotic system using a digit complement. This special case of fixed-point number representation allows us to reduce the silicon area and the number of logic elements to perform the arithmetic operations. The design presents a configurable number of bits, and it is based on the logistic map. The proposed circuit has been implemented on a reconfigurable hardware, FPGA Cyclone V, showing that the number of logic elements has been significantly reduced compared to other works in the literature.

Item Type:	Article
Keywords:	Chaos; Nonlinear dynamics; FPGA synthesis; Computer arithmetic; Digital system;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering Faculty of Science and Engineering > Research Institutes > Hamilton Institute
Item ID:	16728
Identification Number:	https://doi.org/10.1016/j.chaos.2019.01.019
Depositing User:	Erivelton Nepomuceno
Date Deposited:	22 Nov 2022 11:50
Journal or Publication Title:	Chaos, Solitons & Fractals
Publisher:	Elsevier
Refereed:	Yes
URI:	Publisher
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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