Araujo, Túlio and Cardoso, Matheus B.R. and Nepomuceno, Erivelton and Llanos, Carlos H. and Arias-Garcia, Janier (2021) A new floating-point adder FPGA-based implementation using RN-coding of numbers. Computers & Electrical Engineering, 90. p. 106947. ISSN 00457906

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Abstract

A well-known problem in the computer science area is related to numerical data representation, which directly affects adder circuits’ design and a reason to have different formats: IEEE Std. 754, Half-Unit-Biased (HUB), and Round-to-Nearest (RN). RN has an advantage that rounding to nearest is equivalent to a word truncation. It avoids double rounding errors and intermediate rounding steps with an exact conversion between formats, making it applicable to general problems. However, there is a lack of research on the hardware implementation of the RN representation. In this work, we propose hardware architectures for binary and floating-point adders, analyzing for the latter its performance in terms of error and resource consumption in FPGAs. To accomplish this, we have developed a one-bit RN-based adder that allows modular designs, considering an efficient signal propagation to obtain new architectures for both binary and floating-point single-precision adders. The results open new perspectives for further applications.

Item Type:	Article
Keywords:	Round-to-Nearest representation; RN-coding; Floating-point; Adder; FPGA; Hardware;
Academic Unit:	Faculty of Science and Engineering > Electronic Engineering Faculty of Science and Engineering > Research Institutes > Hamilton Institute
Item ID:	16816
Identification Number:	https://doi.org/10.1016/j.compeleceng.2020.106947
Depositing User:	Erivelton Nepomuceno
Date Deposited:	09 Jan 2023 12:14
Journal or Publication Title:	Computers & Electrical Engineering
Publisher:	Elsevier
Refereed:	Yes
URI:	Publisher
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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