Stanojević, Rade (2007) Small active counters. INFOCOM 2007. 26th IEEE International Conference on Computer Communications. IEEE. ISSN 0743-166X

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Abstract

The need for efficient counter architecture has arisen for the following two reasons. Firstly, a number of data streaming algorithms and network management applications require a large number of counters in order to identify important traffic characteristics. And secondly, at high speeds, current memory devices have significant limitations in terms of speed (DRAM) and size (SRAM). For some applications no information on counters is needed on a per-packet basis and several methods have been proposed to handle this problem with low SRAM memory requirements. However, for a number of applications it is essential to have the counter information on every packet arrival. In this paper we propose two, computationally and memory efficient, randomized algorithms for approximating the counter values. We prove that proposed estimators are unbiased and give variance bounds. A case study on Multistage Filters (MSF) over the real Internet traces shows a significant improvement by using the active counters architecture.

Item Type:	Article
Keywords:	Counter architecture; high-speed measurements; Router; Data streaming algorithms; Hamilton Institute
Academic Unit:	Faculty of Science and Engineering > Research Institutes > Hamilton Institute
Item ID:	1682
Depositing User:	Hamilton Editor
Date Deposited:	23 Nov 2009 16:50
Journal or Publication Title:	INFOCOM 2007. 26th IEEE International Conference on Computer Communications. IEEE
Refereed:	Yes
URI:
Use Licence:	This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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