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    Open Loop Approach to Design Low Voltage, 400 mV, 1.3 mW, 10 GHz CMOS Class-B VCO

    Szczepkowski, Grzegorz and Farrell, Ronan (2012) Open Loop Approach to Design Low Voltage, 400 mV, 1.3 mW, 10 GHz CMOS Class-B VCO. In: International Conference on Signals and Electronic Systems 2012, 18-21 September 2012, Wrocław, Poland.

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    The paper presents a method for design of LC cross-coupled oscillators based on an open loop technique and its practical application leading to a high frequency CMOS oscillator prototype. Thanks to the proposed approach, the main circuit parameters such as loaded quality factor (responsible for phase noise performance of LC oscillator) and steady-state oscillation amplitude, can be extracted without the necessity of time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The proposed 130 nm CMOS prototype operates at 10 GHz from a 400m V power supply achieving an average SSB phase noise of -110 dBc/Hz at 1 MHz offset from the carrier and a fractional bandwidth of more than 7.5%. Low average power consumption of 1.3 mW RMS, has been obtained by biasing the oscillator devices to operate in class-B i.e. VGS =VDD =Vth.

    Item Type: Conference or Workshop Item (Paper)
    Keywords: Open Loop Approach; Design Low Voltage;
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Faculty of Science and Engineering > Research Institutes > Institute of Microelectronics and Wireless Systems
    Item ID: 3960
    Depositing User: Ronan Farrell
    Date Deposited: 26 Oct 2012 11:00
    Refereed: Yes
    Funders: Science Foundation Ireland under Grant No. 10/CE/I1853
      Use Licence: This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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