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    A Fully Diff erential Phase-Locked Loop With Reduced Loop Bandwidth Variation

    Collins, Diarmuid (2011) A Fully Diff erential Phase-Locked Loop With Reduced Loop Bandwidth Variation. Masters thesis, National University of Ireland Maynooth.

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    Phase-Locked Loops (PLLs) are essential building blocks to wireless communications as they are responsible for implementing the frequency synthesizer within a wireless transceiver. In order to maintain the rapid pace of development thus far seen in wireless technology, the PLL must develop accordingly to meet the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices. Speci cally this entails meeting stringent noise speci cations imposed by modern wireless standards, meeting low power consumption budgets to prolong battery lifetimes, operating under reduced supply voltages imposed by modern technology nodes and within the noisy environments of complex system-on-chip (SOC) designs, all in addition to consuming as little silicon area as possible. The ability of the PLL to achieve the above is thus key to its continual progress in enabling wireless technology achieve increasingly powerful products which increasingly bene t our daily lives. This thesis furthers the development of PLLs with respect to meeting the challenges imposed upon it by modern wireless technology, in two ways. Firstly, the thesis describes in detail the advantages to be gained through employing a fully di erential PLL. Speci cally, such PLLs are shown to achieve low noise performance, consume less silicon area than their conventional counterparts whilst consuming similar power, and being better suited to the low supply voltages imposed by continual technology downsizing. Secondly, the thesis proposes a sub-banded VCO architecture which, in addition to satisfying simultaneous requirements for large tuning ranges and low phase noise, achieves signi cant reductions in PLL loop bandwidth variation. First and foremost, this improves on the stability of the PLL in addition to improving its dynamic locking behaviour whilst o ering further improvements in overall noise performance. Since the proposed sub-banded architecture requires no additional power over a conventional sub-banded architecture, the solution thus remains attractive to the realm of low power design. These two developments combine to form a fully di erential PLL with reduced loop bandwidth variation. As such, the resulting PLL is well suited to meeting the increasingly demanding requirements imposed on it by today's (and tomorrows) wireless devices, and thus applicable to the continual development of wireless technology in bene tting our daily lives.

    Item Type: Thesis (Masters)
    Keywords: Fully Diff erential Phase-Locked Loop; Reduced Loop Bandwidth Variation;
    Academic Unit: Faculty of Science and Engineering > Electronic Engineering
    Faculty of Science and Engineering > Research Institutes > Institute of Microelectronics and Wireless Systems
    Faculty of Science and Engineering > Research Institutes > Callan Institute
    Item ID: 3984
    Depositing User: IR eTheses
    Date Deposited: 21 Nov 2012 12:12
      Use Licence: This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here

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