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Burke, K., Power, J.A., Donnellan, Brian, Moloney, K. and Lane, W.A. (1994) Worst-case MOSFET parameter extraction for a 2 /spl mu/m CMOS process. In: Proceedings of 1994 IEEE International Conference on Microelectronic Test Structures. IEEE, pp. 119-125. ISBN 0780317572
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Abstract
This paper will describe the process by which realistic nominal and worst-case DC MOSFET model parameter sets were determined and validated for a 2 /spl mu/m CMOS technology. The steps involved in this task, which will be detailed, ranged from the definition of a suitable circuit simulator model, through the collection of statistical parametric data, to the generation and verification of the worst-case model sets obtained from this data.
| Item Type: | Book Section |
|---|---|
| Keywords: | MOSFET circuits; Parameter extraction; CMOS process; Semiconductor device modeling; Equations; CMOS technology; Predictive models; Surface resistance; Circuit simulation; Circuit synthesis; |
| Academic Unit: | Faculty of Social Sciences > School of Business |
| Item ID: | 10784 |
| Identification Number: | 10.1109/ICMTS.1994.303491 |
| Depositing User: | Prof. Brian Donnellan |
| Date Deposited: | 16 May 2019 14:55 |
| Publisher: | IEEE |
| Refereed: | Yes |
| Related URLs: | |
| URI: | https://mural.maynoothuniversity.ie/id/eprint/10784 |
| Use Licence: | This item is available under a Creative Commons Attribution Non Commercial Share Alike Licence (CC BY-NC-SA). Details of this licence are available here |
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