With the rise of interconnected systems, security has become a crucial concern. As a result, there has been a growing interest in developing low-cost embedded cryptographic algorithms that are lightweight and can be integrated into System-on-Chip (SoC) devices. Digital chaotic systems have emerged as a promising approach for building secure communication systems, where various cryptosystems utilize chaotic dynamics to encrypt images into noise-like representations. Recent studies have demonstrated that finite-precision error can be used to derive chaos, which can be systematically applied to encrypt images. However, there is a lack of research on how SoC-based design constraints affect the overall performance of image encryption systems, especially for applications that are sensitive to latency. This study aims to address this gap by presenting an efficient architecture that explores a hardware/software co-design for image encryption based on finite-precision error, specifically designed for resource-limited devices and latency-sensitive applications. Our platform performs the capture and encryption of images with a size of 320 × 240. Using a benchmark image, results show that the developed cryptosystem architecture can encrypt images efficiently while offering low hardware occupation.