In this paper a new technique of utilizing parallel sigma delta modulation for high frequency switch mode digital power amplifiers is presented. This approach allows achieving a factor of two increase of a digital logic speed for band-pass SDM with minor adjustments made. A universal scheme for a SDM system transformation is provided. Since the transformation scheme is established, a parallel low-pass SDM, expandable to a factor of four clock frequency reduction is designed. The parallelization of a low pass SDM however requires modification on the form of a Noise Transfer Function in order to preserve desired speed of a digital logic. This can affect the overall performance of the SDM. The derivation of the systems is provided through analysis of discrete time domain equations. The method is validated through simulations.