Semiconductor wafer etching is, to a large extent, an open-loop process with little direct feedback control. Most silicon chip manufacturers rely on the rigorous adherence to a “recipe” for the various etch processes, which have been built up based on considerable historical experience. However, residue buildup and difficulties in achieving consistent preventative maintenance operations lead to drifts and step changes in process characteristics. This paper examines the particular technical difficulties encountered in achieving consistency in the etching of semiconductor wafers and documents the range of estimation and control techniques currently available to address these difficulties. An important feature of such an assessment is the range of measurement options available if closed-loop control is to be achieved.